Target technology
FPGA
ASIC
FPGA vendor
AMD / Xilinx: Artix, Kintex, Virtex, Zynq
Intel / Altera: Cyclone, Arria, Stratix
Lattice: ECP5, iCE40, Nexus
Microchip / Microsemi: PolarFire, IGLOO
Gowin: GW1N, GW2A
Efinix: Trion, Titanium
QuickLogic: EOS, PolarPro
Generic FPGA
Device / family (optional)
ASIC technology
Generic standard-cell
TSMC GlobalFoundries
Samsung Foundry UMC
SkyWater 130nm (open PDK) Intel Foundry
Process node (optional)
Clock name
Reset type
Synchronous Asynchronous
Reset polarity
Active-high Active-low
Reset name
Clocking notes (optional: multi-clock / CDC)
Target Fmax (MHz, optional)
Area priority
Balanced Minimize area Not critical
Power priority
Balanced Minimize power Not critical
End application (drives PPA bias)
HDL language
SystemVerilog Verilog VHDL
Version
Max repair iterations
4 (recommended) 3 2 1 draft only VHDL: generation is supported now; functional verification for VHDL (GHDL) is rolling out. Verilog & SystemVerilog run the full verified loop.