Anyone can wrap an AI model around "write me some Verilog." The hard, defensible part is the closed loop: real simulation, reliable failure analysis, and repair that actually converges.
Engineering agents coordinate; a deterministic engine does the real work. An orchestrator enforces a bounded iteration budget so every run terminates - and ends with the engineer reviewing the result.
The simulation and synthesis layer is plain, sandboxed tooling - not a model. Loop reliability lives here, with timeouts and safety checks on every run.
Testbenches are generated to report their own pass/fail outcome, so a parser scores every run automatically - no human watching waveforms.
On failure the loop localizes the issue and decides whether the design or the testbench is at fault before fixing the right one - and stops within a budget.
A small set of focused roles, each handing off to the next - and to the deterministic engine that grounds them.
Turns a natural-language or structured spec into a formal intent - interfaces, protocol, timing, and the corner cases that matter.
Produces synthesizable RTL with a synthesizability critic, biased toward area or timing for your target and application.
Generates a self-checking testbench with directed and constrained-random cases, assertions, and a reference model.
Reads failing results, localizes the fault, and patches the right artifact - the genuinely hard, defensible part of the loop.
A benchmark suite of standard blocks with known-good references measures convergence rate and time-saved versus a baseline - and every run becomes a proprietary spec → RTL → bug → fix trace.
Convergence and bug-find rates on a fixed benchmark - the number that proves the loop works.
Each iteration logged from day one becomes training and evaluation data competitors don't have.
A max-iteration budget guarantees termination; the engine sandboxes and times out every simulation.
Pick a block, give it a spec, and watch each stage stream live.