Verification-first AI for chip design

From spec to verified RTL,
on autopilot.

Nexeda is an AI copilot for FPGA & ASIC engineers. It reviews your RTL, writes self-checking testbenches, and generates synthesizable Verilog — then iterates spec → simulate → repair until every functional case passes.

Try the live loop → See how it works

No setup. Runs on open simulators (Icarus, Verilator, yosys) — Vivado & on-prem on the roadmap.

# spec → sync_fifo (WIDTH=8, DEPTH=16), target: Xilinx FPGA iter 1 designing rtl ............... ok iter 1 building self-checking tb ... ok iter 1 simulate .................... 31/34 checks FAIL: random_fifo_order iter 2 debug → root cause: count not held on simultaneous r/w iter 2 repair design → re-simulate . 34/34 checks ✓ ppa yosys synth_xilinx ......... LUTs=78 FFs=140 SIGN-OFF

Why Nexeda

Verification is 70% of the work.
We close the loop.

Most AI tools stop at "here's some Verilog." That leaves the hard part — proving it's correct — on you. Nexeda treats verification as the product: every line it touches is simulated, checked against assertions, and repaired until it passes.

🔍

Review first, generate later

Point Nexeda at existing RTL and it finds bugs, inferred latches, CDC and reset risks, and proposes SVA assertions — the lowest-risk way to build trust.

✓

Self-checking by default

Generated testbenches report PASS/FAIL per case and a coverage summary. No eyeballing waveforms — the loop scores itself.

♻️

Closed-loop repair

On failure, the debugger localizes the fault, decides whether the design or the testbench is wrong, fixes it, and re-runs — within a bounded budget.

The agentic loop

Five agents, one sign-off

A deterministic tool runner wraps real simulators; the LLM agents only coordinate. That's what makes the loop reliable instead of a guess.

Interpret

Spec → formal intent: ports, protocol, timing, corner cases.

Design

Synthesizable Verilog, PPA-biased to your target & application.

Verify

Self-checking testbench + SVA + functional coverage.

Simulate & repair

Run, parse failures, fix design or TB, iterate to convergence.

Sign-off + PPA

All checks pass → utilization & Fmax estimate via synthesis.

Walk through the architecture →

RTL Review

Catch the bugs before silicon does

Lint + structural analysis + an AI reviewer that reads intent. Get specific, cited findings and ready-to-paste assertions — not vague suggestions.

Inferred latches, incomplete sensitivity, multi-driven nets
Clock-domain crossing & reset hazards
Auto-generated SVA to lock down invariants

// Nexeda review · severity: medium FINDING latch inferred on `next_state` └ default branch missing in always @(*) case FINDING CDC: `busy` sampled across clk domains └ add 2-FF synchronizer ASSERT property: full & empty never both high assert property (@(posedge clk) !(full & empty));

Generate & verify

Standard blocks, signed off in minutes

Describe a FIFO, arbiter, AXI-Lite slave or FSM in plain language. Nexeda produces lint-clean RTL, verifies it against a self-checking bench, and reports FPGA utilization — all in one run.

Synthesizable Verilog-2012, parameterized & commented
Directed + constrained-random testing
PPA estimate (LUT/FF/Fmax) on every sign-off

module sync_fifo #(parameter WIDTH=8, DEPTH=16)( input clk, rst, wr_en, rd_en, input [WIDTH-1:0] din, output reg [WIDTH-1:0] dout, output full, empty, output reg [$clog2(DEPTH):0] count ); // ... synthesizable, lint-clean, verified ✓

Built to measure

An eval harness at the core

Every run is logged as a spec → RTL → bug → fix trace. The benchmark suite is how we prove progress — and the dataset that compounds over time.

coordinated agents in the loop

100%

runs scored automatically, no manual waveform review

FPGA→ASIC

FPGA-first today, ASIC flow on the roadmap

Watch an RTL design verify itself

Give Nexeda a spec and watch the loop run live — generate, simulate, repair, sign off.

Open the Playground Read the vision

From spec to verified RTL,on autopilot.

Verification is 70% of the work.We close the loop.